Editor's Note: Although the primary target market for the 86100CU-400 application presented below is for ASIC/SoC designs, I'm assured by the folks at Agilent that this application is also applicable ...

Learn about the working principles of Phase-Locked Loops (PLL) and why they are widely used for applications where frequency tracking, resonance driving, and oscillator control are required.

IC designer Don Sauer saw my blog about the difficulties of simulating PLLs and sent me a SPICE file (zip) of a basic PLL that you can play with. Don writes: I have a simple spice netlist for a PLL ...

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...

If you want a stable oscillator, you usually think of using a crystal. The piezoelectric qualities of quartz means that it can be cut in a particular way that it will oscillate at a very precise ...

Phase-locked loops (PLLs) are indispensable timing and frequency synthesis circuits, finding application in communication transceivers, clock distribution, navigation receivers and sensor interfaces.

Some brief theory and typical measurements of phase noise. How to produce the lowest phase noise at a PLL output. A standard design procedure for a typical Type 2, second-order loop. As stated in ...

When Hackaday runs a contest, we see all manner of clever projects. But inevitably there are some we don’t see, because their builders didn’t manage to get them finished in time. [Park Frazer]’s phase ...

The ARKCHIPS PLL is a versatile and stable general-purpose frequency synthesizer with phase synchronization (de-skew) Phase-Locked Loop (PLL) : feed ...

The total power consumption of the proposed PLL is only 8.89 mW from a 1 V supply, which leads to a figure of merit of reference of -247.4 dB. Credit must be given to the creator. Only noncommercial ...